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Design of Image Compression Based VLSI Architecture for the Implementation of 2-D DWT

Sruthi Menon .C, C. Thirumaraiselvi, Dr.R. Sudhakar

Abstract


In this paper, a new data access scheme for the computation of lifting 2-D DWT (Discrete Wavelet Transform) using systolic arrays with block processing is suggested. From DG (dependence graph) linear systolic array is directly derived. For parallel and pipeline implementation of 1-D DWT from suitably segmented DG is used for deriving 2-D systolic arrays. Above two systolic arrays are used as building blocks to derive the lifting 2-D DWT.The proposed architecture requires a small on-chip memory of (4N + 8P) where N is the image width, process a block of P samples in every cycle. Compared to existing structures it has high throughput, low latency and less computational complexity. The synthesis is performed in Xilinx 8.1i, Spartan 2E hardware with XC2S50E device and FT256 package and simulation results are obtained using Mat lab 7.10 and modelsim 6.3f.The image size is 512 X 512 and block size is 4 with area is 987500.22 u.sqm, power consumed is 8.34027 mw and delay count is 16.11 ns.

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