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IEEE-754 Quadruple Precision Floating Point Core Verilog

P.Sankara Rao

Abstract


A floating point processing system which uses a multiplier unit and an adder unit to perform properly rounded quad precision floating point arithmetic operations using double-extended hardware. The floating point processing system includes quad data muxes for converting a quantity between quad precision representation and two double-extended precision quantities and vice versa, wherein the sum, if added at infinite precision, of the two double-extended precision quantities is equal to the quad precision quantity. The floating point processing system further includes hardware for performing arithmetic operations on double-extended precision quantities. Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point arithmetic logic unit that also supports two parallel double precision addition, subtraction, multiplication and division. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware that a fully parallel quadruple precision multiplier. With this implementation, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have a latency of only two cycles. The design is pipelined so that two double precision multiplications can be started every cycle or a quadruple precision multiplication can be started every other cycle. This paper gives digital design and architecture for 128 bit floating point arithmetic operations. The Core has been designed and implemented using VERILOG code and simulated using modelsim.

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