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Specific Power Illustration of 4T SRAM Cell Using 45 nm technology

Sushil Bhushan, Shyam Akashe

Abstract


This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 30.83% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. Cadence Virtuoso simulation in standard 180nm CMOS technology confirms all results obtained from this paper.

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