-->

DESIGN VHDL OF A RECONFIGURABLE HMAC-HASH UNIT

Vandana parihar

Abstract


In this paper, a design VHDL of a reconfigurable HMIAC-hash unit is discussed. This unit implements one OF four standard hash algorithms, namely, MD5, SHA-1, RIPEMD- 160, HMAC-MD5, HMAC-SHA- The design VHDL exploration of this unit is done using the language. We propose key reuse mechanism for successive messages in order to improve the HMAC throughput. In Addition, we explore the design space by providing two Implementations of the HMAC algorithm, one for ageneral key size and another for a fixed key size. In each Implementation, we use standard key use and the proposed Key reuse mechanisms, and that results in four different Implementations. The performance of these four Implementations is analyzed with respect to three design Metrics: area, delay, and throughput. We found that the proposed key reuse mechanism improves the HMAC Throughput significantly when a large key is reused

Full Text:

PDF

Refbacks

  • There are currently no refbacks.